1. Field of the Invention
The present invention relates to a serial access memory, and particularly to transfer units set as paths used when data stored in memory cells are respectively transferred to read and write registers.
2. Description of the Related Art
Each of memory blocks of a serial access memory adopts a configuration wherein read registers and write registers are respectively added to memory cells of a DRAM. The memory capacity of such a memory block is normally taken up or configured in units of 256 Kbits or 512 Kbits, for example to ensure an operating margin for each memory and reduce the peak of current consumption. Since the serial access memory often deals with image data, it needs to have a capacity of a few Mbits. In order to implement it through the use of the above memory block, the serial access memory is made up of a plurality of memory blocks.
With the recent scale-down technology, the memory cell can be formed greatly by shortening it. However, the read registers and write registers are not scaled down in a manner similar to the memory cells. Thus, although the occupied area of each memory cell in a memory block is reduced, the read registers and write registers are not so scaled down. Accordingly, a problem arises in that the serial access memory has not yet been scaled down in chip size as might be expected. Further, since the conventional serial access memory comprises the plurality of memory blocks including the write and read registers, circuits for controlling the respective registers and transfer units increase in number, thus increasing current consumption.
An object of the present invention is to provide a serial access memory low in current consumption, which is capable of restraining an increase in chip size even if memory capacity increases.
A serial access memory of the present invention comprises first and second memory arrays. The first memory array includes first memory cells, first sense amplifiers and pairs of first bit lines connected to the first memory cells and the first sense amplifiers. The second memory array includes second memory cells, second sense amplifiers and second bit lines connected to the second memory cells and the second sense amplifiers. The serial memory further comprises pairs of column lines each of which is connected to one of the pairs of first bit lines and one of the pairs of the second bit lines, write registers each of which is connected to one of the pairs of column lines, a write address accessing circuit connected to the write registers for selecting one of said write registers, read registers each of which is connected to one of the pairs of column lines, a read address accessing circuit connected to the read registers for selecting one of the read registers, an input circuit connected to the write registers, and an output circuit connected to the write registers.